UPD44646363AF5-E22-FQ1-A【PDF 28/42 页】SRAM DDRII 72MBIT 165-PBGA

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μ PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A

Scan Register Definition (1)

Register name

Instruction register

Bypass register

ID register

Boundary register

Description

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Boundary register

Bit size

3

1

32

109

Unit

bit

bit

bit

bit

ID Register Definition

2.0 Clock Cycles Read Latency

Part number

Organization

ID [31:28] vendor revision no.

ID [27:12] part no.

ID [11:1] vendor ID no. ID [0] fix bit

μ PD44646092A-A

μ PD44646182A-A

μ PD44646362A-A

8M x 9

4M x 18

2M x 36

XXXX

XXXX

XXXX

0000 0000 1000 1100

0000 0000 1000 1101

0000 0000 1000 1110

00000010000

00000010000

00000010000

1

1

1

2.5 Clock Cycles Read Latency

Part number

Organization

ID [31:28] vendor revision no.

ID [27:12] part no.

ID [11:1] vendor ID no. ID [0] fix bit

μ PD44646093A-A

μ PD44646183A-A

μ PD44646363A-A

8M x 9

4M x 18

2M x 36

XXXX

XXXX

XXXX

0000 0000 1001 1000

0000 0000 1001 1001

0000 0000 1001 1010

00000010000

00000010000

00000010000

1

1

1

26

Data Sheet M19960EJ2V0DS

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